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Data-Driven Networking Architecture Lab
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The lab studies networking, down to the circuit level, using data-driven processors.
AboutAbout the lab
Executing processing passively, triggered by the arrival of data.
The Data-Driven Networking Architecture Lab studies networking mechanisms centered on data-driven processors, which advance processing when data arrives.
The lab covers networking methods, processor architecture, and circuit implementation in one consistent line of research.
A data-driven processor is a non-von Neumann processor that can execute an operation once its input data are all available, and it is inherently well suited to parallel processing.
It is a small lab where students work closely with the professor, and there are no core hours.
Key terms
- Data-driven processor
- A processor that executes operations as soon as their input data are all available. Its operating principle is inherently well suited to parallel processing.
- Non-von Neumann
- A type of processor that works differently from sequential (von Neumann) processors, which execute instructions one after another. The data-driven approach falls into this category.
- FPGA
- A commercially available chip whose circuit configuration can be rewritten. This lab uses it to implement and evaluate circuits.
- Self-timed pipeline
- A pipeline circuit that operates without a clock shared across the whole circuit (a global clock).
NewsLab news
Lab information sessions for academic year 2026 were held (Oct 13, Oct 21, and Oct 27)
A paper by a master's student won the Best Paper Award at IEEE CCWC 2025
ResearchResearch themes
The Data-Driven Networking Architecture Lab studies everything from networking methods to circuit implementation methods, centered on data-driven processors that execute processing when data arrives. The lab handles the whole process, from designing processing methods to implementing and evaluating circuits on FPGAs.
*Illustrative imageNetworking Centered on Data-Driven Processors
Even as the number of packets processed at the same time increases, a data-driven processor keeps processing time constant as long as the load does not exceed the design target, which guarantees real-time processing. Because this property suits networking processing, the lab studies everything from methods to circuit implementation.
*Illustrative imageDesign of Self-Timed Pipelines for FPGAs
The lab has studied circuit design methods for implementing a two-phase bundled-data ring self-timed pipeline on commercially available FPGAs. It presents an improvement that adds shortcuts to the paths of the main transfer control signals to increase throughput, and it shows the timing constraints required for static timing analysis.
*Illustrative imageImplementation of a Data-Driven Processor for IoT
The lab has presented the implementation of "STDDP," a processor that performs real-time multiplexed processing on a self-timed pipeline circuit. It defined an instruction set with reference to RV32I, the RISC-V base integer instruction set, and evaluates a processor that implements it.
*Illustrative imageA Processing Method That Guarantees Throughput for IoT Devices
The lab has pointed out a problem with the data-driven approach: when the number of data items flowing through the processor exceeds its capacity, the expected throughput can no longer be obtained. It proposes the "Stream-Thru processing method" to solve this problem.
MembersFaculty
The members of the Data-Driven Networking Architecture Lab are faculty members and students in the doctoral program and the master's program.As of 2026
- Associate ProfessorShuji Sannomiya
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Report an errorAbout the images
The top and research theme images are illustrative and were not taken at the lab. They are cropped from Wikimedia Commons images. Cropped CC BY-SA images are provided under the same CC BY-SA license as the original (version shown on each line).
- Top image: “Mojo v3 FPGA Development Board ( )” SparkFun Electronics from Boulder, USA / CC BY 2.0 (cropped)
- Networking Centered on Data-Driven Processors: “Optic fiber cables 02” SwarmCheng / CC BY-SA 4.0 (cropped)
- Design of Self-Timed Pipelines for FPGAs: “Computer motherboard 11” Kurt Kaiser / CC0 (cropped)
- Implementation of a Data-Driven Processor for IoT: “RISC V prototype chip - closeup” Derrick Coetzee (User:Dcoetzee) / CC0 (cropped)
- A Processing Method That Guarantees Throughput for IoT Devices: “Teensy++ 2.0 microcontroller” www.sparkfun.com / CC BY-SA 3.0 (cropped)
- Related lab (High Performance Computing Systems Lab): “Supercomputer Quinde I” JeffCF03 / CC BY-SA 4.0 (cropped)
- Related lab (Mathematical Informatics Lab): “Galileo supercomputer rack” CINECA / CC BY 2.0 (cropped)
- Related lab (High-Efficiency Custom Circuit Design Engineering Lab (Lila.CS)): “ML34003P” Mister rf / CC BY-SA 4.0 (cropped)
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