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Electronic Equipment Engineering Lab
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The lab studies bonding technology that joins dissimilar materials at low and room temperatures.
AboutAbout the lab
Packaging dissimilar materials to build compact, highly functional integrated devices
The Higurashi-Takeuchi Lab studies heterogeneous integration technology, which integrates dissimilar materials and dissimilar functions, and low-temperature bonding technology.
In the semiconductor field, multifunctionality and the fusion of different functions are advancing alongside miniaturization, and the integration of dissimilar materials is attracting attention as a key to the continued growth of the semiconductor industry.
The lab aims to contribute to creating electronic and optical devices, sensors, actuators, and energy devices that are compact, high-performance, and energy-efficient.
It also aims to contribute to advancing the electronic equipment systems that will support the future IoT society.
Key terms
- Heterogeneous integration
- A technology that combines components with different materials or functions into a single device
- Surface activated bonding
- A room-temperature bonding technique that joins materials to each other at room temperature
- Polysilazane
- A polymer material known as a precursor of SiO2. It is also known as a glass coating for car bodies
NewsLab news
Established "T-CHIPS," a consortium for advanced semiconductor packaging and heterogeneous integration technology
"Development Trends and Reliability Evaluation of Bonding Technologies and Materials for Semiconductor Devices," a book with a chapter co-authored by Professor Higurashi, was published
A paper by doctoral students and others was published in Ceramics International
A doctoral student received the Academic Plaza Award from the Japan Institute of Electronics Packaging
ResearchResearch themes
The lab aims to contribute to creating functional devices that are compact, high-performance, and energy-efficient, using bonding technology that joins dissimilar materials at low and room temperatures. Its research covers packaging by surface activated bonding, smoothing of rough bonding surfaces, bonding via polysilazane, and hollow Au bumps.
*Illustrative imageDevice packaging by surface activated bonding
Bonding is the cornerstone of electronic device packaging. Low-temperature and room-temperature bonding cause little damage to devices and make it possible to integrate materials with different coefficients of thermal expansion and polymers with low heat resistance. The lab studies device packaging that applies surface activated bonding.
*Illustrative imageSmoothing rough surfaces for room-temperature bonding
For materials that are difficult to polish, such as chip-sized pieces, patterned films, and Au, the lab develops a smoothing technique based on additive processing. By combining template stripping, a transfer technique for thin metal films, with surface activated bonding, it makes room-temperature bonding possible even for rough surfaces.
*Illustrative imageRoom-temperature bonding via polysilazane
Polysilazane, known as a precursor of SiO2, is converted into SiO2 at the bonding interface and combined with plasma hydrophilization treatment, achieving bonding at room temperature. The lab realizes wafer bonding with good adhesion and high bonding strength through a room-temperature process.
*Illustrative imageLow-temperature, low-load bonding with hollow Au bumps
Sharp-tipped Au micro-bumps, whose tips plastically deform and promote low-temperature bonding, have the problem that stress concentration at the tip can damage the chip. With hollow bumps made by Au film transfer, the bumps plastically deform under a lower load than before, reducing stress concentration and achieving low-temperature, low-load bonding.
MembersFaculty
The Higurashi-Takeuchi Lab consists of faculty members, master's and undergraduate students, and technical assistants.As of 2026
- ProfessorEiji Higurashi
- Associate ProfessorKai Takeuchi
- Assistant ProfessorShintaro Goto
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Report an errorAbout the images
The top and research theme images are illustrative and were not taken at the lab. They are cropped from Wikimedia Commons images. Cropped CC BY-SA images are provided under the same CC BY-SA license as the original (version shown on each line).
- Top image: “A semiconductor wafer on a dicing (blue) tape. Few chips (dies) from the wafer have already been picked up (removed) for further manufacturing” Khpsoi / CC BY-SA 4.0 (cropped)
- Device packaging by surface activated bonding: “3x3 Quilt Packaging Chip Array” Jacksontlu / CC BY-SA 4.0 (cropped)
- Smoothing rough surfaces for room-temperature bonding: “Multicrystalline silicon wafer with thin film iridescence” Radiotrefoil / CC BY-SA 4.0 (cropped)
- Room-temperature bonding via polysilazane: “IMaGe 31072R – Silicon Wafer 20120926” Rob Bulmahn / CC BY 2.0 (cropped)
- Low-temperature, low-load bonding with hollow Au bumps: “MAC01” Mister rf / CC BY-SA 4.0 (cropped)
- Related lab (Takeuchi Lab): “Hero-64-pixel-array-superconducting-nanowire-single-photon-detector-b” NASA/JPL-Caltech; Text by Dr. Warren Holmes / Public domain (cropped)
- Related lab (Next-Generation Spin Electronics Materials Engineering [Tsunoda] Lab): “Actuator arm assembly of a hard disk drive” Mk2010 / CC BY 4.0 (cropped)
- Related lab (Green Power Electronics [Endoh (T.)] Lab): “Wafer scale integrated circuit on 300 mm wafer” Wikideas1 / CC0 (cropped)
- Related lab (Innovative Spintronics Device Lab): “Unisys SCAMP die” Pauli Rautakorpi / CC BY 3.0 (cropped)
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