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Fukushima Lab
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The lab researches three-dimensional integration, which stacks semiconductor chips vertically.
AboutAbout the lab
Changing the future of semiconductors through holistic integration engineering that takes a bird's-eye view
The Fukushima Lab researches three-dimensional integration (3D-IC) technology, which stacks semiconductor chips vertically.
Chips are thinned to a few tens of micrometers, and the upper and lower chips are connected by thin wiring that passes through the silicon.
The lab introduces this technology as also being used in the high-capacity memory of GPU modules for generative AI.
It also works on applications in medicine and wearables, such as devices that embed chips in flexible substrates.
Key terms
- Three-dimensional integration (3D-IC)
- A form that stacks integrated circuit chips vertically to achieve higher density and smaller size.
- TSV
- Through-silicon via. Thin wiring that passes vertically through a thinned chip and electrically connects the chips above and below.
- Hybrid bonding
- Bonding that joins copper and insulating-film surfaces simultaneously at the atomic level, without solder.
NewsLab news
A book to which Prof. Fukushima contributed chapters, "Handotai Gijutsu Shiryoshu" (a reference collection on semiconductor technology), was published
A co-authored paper was accepted by Japanese Journal of Applied Physics
A co-authored paper on hybrid bonding was accepted by IEEE Transactions on Components, Packaging and Manufacturing Technology
A book to which Prof. Fukushima contributed chapters, "Jisedai ni Muketa Handotai Pakkeijingu Gijutsu" (semiconductor packaging technologies for the next generation), was published
ResearchResearch themes
The lab works on process and materials technologies for building three-dimensionally stacked integrated circuits (3D-ICs). Aiming at 3D-ICs applicable to a full-fledged AI society, it conducts research on micro/nano fabrication engineering and semiconductor packaging engineering.
*Illustrative image3D Integration: Stacking Chips Vertically
The lab makes thin wiring that passes through silicon, the base material of chips (TSVs), and stacks chips thinned to a few tens of micrometers. It researches technology that takes already-fabricated flat integrated circuits and makes them three-dimensional.
*Illustrative imageHybrid Bonding
This is a technology that bonds copper to copper and the surrounding insulating films to each other simultaneously at the atomic level, without solder microbumps. The lab researches methods such as surface activation with radicals and lowering the bonding temperature, in collaboration with companies.
*Illustrative imageChip-to-Wafer Integration and Self-Assembly
In chip-to-wafer integration, where only chips confirmed to be good are stacked on a wafer, mounting chips one by one takes time. The lab addresses this problem with self-assembly mounting, in which chips align themselves using the surface tension of water droplets.
*Illustrative imageFlexible Integrated Devices (FHE)
This is research on flexible hybrid electronics (FHE). Small divided chips (dielets) are embedded in a flexible substrate and connected with fine wiring, achieving both performance and flexibility. The lab has built devices such as µLED displays, artificial retinas, and pulse-wave sensors worn on the fingernail.
MembersFaculty
The Fukushima Lab's members include faculty, academic researchers, commissioned researchers from companies, and doctoral, master's, and undergraduate students.As of 2026
- ProfessorTakafumi Fukushima
- Assistant ProfessorSanghoon Lee
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Report an errorAbout the images
The top and research theme images are illustrative and were not taken at the lab. They are cropped from Wikimedia Commons images. Cropped CC BY-SA images are provided under the same CC BY-SA license as the original (version shown on each line).
- Top image: “MF30011R 1702-2 die” Mister rf / CC BY-SA 4.0 (cropped)
- 3D Integration: Stacking Chips Vertically: “Silicon chip from a computer laser mouse under a microscope 50х” Original: Alexander Klepnev Derivative work: IamMM / CC BY-SA 4.0 (cropped)
- Hybrid Bonding: “Clean room” Uploaded by Duk 08:45, 16 Feb 2005 (UTC) / Public domain (cropped)
- Chip-to-Wafer Integration and Self-Assembly: “A semiconductor wafer on a dicing (blue) tape. Few chips (dies) from the wafer have already been picked up (removed) for further manufacturing” Khpsoi / CC BY-SA 4.0 (cropped)
- Flexible Integrated Devices (FHE): “Flexible display” U.S. Army RDECOM / CC BY 2.0 (cropped)
- Related lab (Tanaka-Vergara-Guo Lab): “AE National Semiconductor B9212 GAL16V8QS-25QNC c AST B AD” Epop / CC BY-SA 3.0 (cropped)
- Related lab (Tsukamoto Lab): “Integrated-circuit-open” 作者不詳 / Public domain (cropped)
- Related lab (Mizoshiri Lab): “Зеркало резонатора волоконного лазера Er ZBLAN и его рабочее волокно (Resonator mirror of Er ZBLAN fiber laser and its working fiber)” Hius1 / CC BY 4.0 (cropped)
- Related lab (Biwa Lab): “Flame-tube-resonance-overlay” MikeRun / CC BY-SA 4.0 (cropped)
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