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小菅研究室（Klab）
Showing the original Japanese · View translation
AIの電力問題に、脳をまねたチップと3次元集積で挑む研究室。
AboutAbout the lab
AI処理を進化させる次世代の集積回路
小菅研究室は、
AIは
この
チップ実装技術や
Key terms
- 布線論理型プロセッサ
- 計算の
中身を 配線 その ものとして 回路に 作り込み、 メモリとの やりとりを 減らした プロセッサ - ニューラルネットワーク
- 脳の
神経細胞の つながりを まねた 計算の 仕組み。 今の AI技術のもとになっている - 3次元集積
- 複数の
半導体チップを 縦に 重ね、 チップどうしを 短い 配線で つなぐ 技術
NewsLab news
博士課程の
学生が、 VLSI Symposium 2026 で Best Student Paper Award Finalist に 選出 小菅准教授が、
電気通信普及財団賞 奨励賞を 受賞 TSMCとの
AIプロセッサの 共同研究成果が、 IEEE Transactions on Circuits and Systems-I に 採択 博士課程の
学生の 低コストAIプロセッサに 関する 論文が、 OJCAS に 掲載 研究室配属や
志望受験生向けの Webページを 公開
ResearchResearch themes
AI処理に
*Illustrative image脳をまねた低電力AIプロセッサ
ニューラルネットワークの
*Illustrative imageチップを重ねる3次元集積
メモリや
MembersFaculty
小菅研究室の
- Associate Professor小菅 敦丈Publications ↗
- Project Professor濱田 基嗣
VoicesStudent voices
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Report an errorAbout the images
The top and research theme images are illustrative and were not taken at the lab. They are cropped from Wikimedia Commons images. Cropped CC BY-SA images are provided under the same CC BY-SA license as the original (version shown on each line).
- Top image: “Intel@14nm@Skylake@Skylake-SP(XCC)@Xeon(ES)@QJW5 DSCx8 poly@20x - Flickr - FritzchensFritz” Fritzchens Fritz from Berlin / CC0 (cropped)
- 脳を
まねた 低電力AIプロセッサ: “Neuromorphic Nanowire Network Chip Wirebonded to Chip Carrier” DrHughManning / CC BY-SA 4.0 (cropped) - チップを
重ねる 3次元集積: “Stacked Turing Chips TU104 TU106 TU116 DSC08577-DSC )” Fritzchens Fritz from Berlin / CC0 (cropped) - Related lab (飯塚研究室): “07R01” Mister rf / CC BY-SA 4.0 (cropped)
- Related lab (池田研究室): “Silicon chip from a computer laser mouse under a microscope 50х” Original: Alexander Klepnev Derivative work: IamMM / CC BY-SA 4.0 (cropped)
- Related lab (入江・門本研究室): “12-inch silicon wafer” Peellden / CC BY-SA 3.0 (cropped)
- Related lab (竹内研究室): “Datacenter Server Racks ( )” Carl Lender / CC BY 2.0 (cropped)
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