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Kobayashi Lab
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The lab researches supercomputers that speed up computation using accelerators such as GPUs.
AboutAbout the lab
Speed is justice in computer science.
The Kobayashi Lab studies massively parallel computer systems and methods for solving real problems with them.
At its center is high-performance computing using accelerators, beginning with GPUs.
Because the power available to supercomputers is limited, improving energy efficiency has become an urgent issue.
From system configuration and algorithms to execution scheduling, the lab builds mechanisms that draw out performance from both the hardware and software sides.
Key terms
- High-performance computing
- Technology that runs many computers at the same time to finish large computations in a short time. Also called HPC
- Accelerator
- A device that performs certain computations quickly in place of the CPU. Examples include GPUs and FPGAs
- GNN
- A type of neural network (graph neural network) that learns from data represented as graphs of connected points and lines
NewsLab news
A paper with a student as first author was accepted to a workshop at ICPP 2026
A paper from joint research with the University of Tsukuba and Komazawa University was published in an academic journal
The AC2 Lab was launched
ResearchResearch themes
The lab studies AI and HPC systems that are sparse, irregular, and sensitive to the effects of communication. Its long-term goal is to establish principles for keeping running on accelerators those workloads whose efficiency depends not only on the amount of computation but also on scattered memory access, data movement, and the way synchronization is done.
*Illustrative imageWafer-Scale Computers and Graph Learning
The lab is investigating GNN training on wafer-scale computers. On computers built from many GPUs, irregular memory access and the burden of distributed memory reduce efficiency, so the lab seeks to determine for which kinds of graph learning this approach, with its simple execution model and large high-speed memory, has the advantage.
*Illustrative imageCompression and Offloading of Inter-GPU Communication
When training large language models on multiple GPUs, communication becomes a bottleneck when scaling up. The lab is investigating how much the overall training speed can be improved by compressing the data to be communicated on devices called DPUs and having them take over the communication.
*Illustrative imageRuntimes That Support Irregular Computation
The lab is considering how to assign sparse, irregular, communication-sensitive workloads to GPU clusters, to systems combining GPUs and DPUs, and to wafer-scale computers. It aims to turn shifting dependencies into clues for deciding data placement, communication, and execution order.
MembersFaculty
The members of the Kobayashi Lab are faculty members and master's students.As of 2026
- Associate ProfessorRyohei KobayashiPublications ↗
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Report an errorAbout the images
The top and research theme images are illustrative and were not taken at the lab. They are cropped from Wikimedia Commons images. Cropped CC BY-SA images are provided under the same CC BY-SA license as the original (version shown on each line).
- Top image: “Pleiades two row” NASA Ames Research Center / Public domain (cropped)
- Wafer-Scale Computers and Graph Learning: “12-inch silicon wafer” Peellden / CC BY-SA 3.0 (cropped)
- Compression and Offloading of Inter-GPU Communication: “RibbonCutout1” Infestor / CC BY-SA 4.0 (cropped)
- Runtimes That Support Irregular Computation: “SocialNetworkAnalysis” Martin Grandjean / CC BY-SA 4.0 (cropped)
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